In digital communications systems, it is critical to synchronize the data timing between transmit and receive stations in order to achieve highly efficient data link performance. Typically, receivers in such systems continuously monitor for signals using circuits that recover the data clock timing. Once the clock has been detected within a signal, the data is isolated and analyzed to determine the synchronization of the data message, which allows the signal to be decoded by the receiver. In systems with a transmitted modulation signal that is always present, or the transmissions are of long duration, techniques, such as the Costas Loop and Kalman filtering, are available to achieve and maintain accurate data timing synchronization.
However, in a TDMA communication system, particularly when the transmissions are of very short duration and occur at a high bit rate, many of the existing techniques for achieving accurate data timing synchronization are not feasible, produce unacceptably poor results and/or are characteristically inefficient. For instance, the output from the receiver can be continuously sampled, the data stored and statistically analyzed in real-time in an attempt to isolate and determine the timing of the short duration (i.e., burst) TDMA communication. This type of scheme is typically implemented using conventional brute force DSP techniques. The drawback of this type of data timing synchronization is that it is typically inefficient and implementation is costly.
In order to properly conduct data timing synchronization in the TDMA burst communication system it is necessary to eliminate the effect of the receiver bias voltage on the analog baseband output signal. The discriminator serves to convert the frequency deviation of the received signal into a voltage variation vs. time, along with a bias voltage. This bias voltage is subject to variation due to temperature, component aging, and other factors. These variations or offsets in the bias voltage adversely affect the ability of the data detection circuit to accurately convert the time-varying voltage into detected bits. More specifically, as offset bias voltage varies, the ideal received bit detection threshold of the discriminator drifts away from the center value, which has a tendency to cause an increase in the bit error rate. Because such systems operate at a megabit data rate, even slight drifts off center in the data bit threshold of the discriminator results in the loss of data.
Therefore, an unsatisfied need exits for a system and method for optimally adjusting the received bit detection threshold in a TDMA burst communication system. In such communication systems, once the received bit detection threshold has been adjusted, then determining the time synchronization becomes a much easier task, because sampling with the correct offset allows the receiver's synchronization process to solve for only the time uncertainty. Such a system and method should result in a simplified process that eliminates the need to implement sampling and/or post-processing of the analog baseband output signal.